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d a t a sh eet preliminary speci?cation file under integrated circuits, ic02 1996 may 21 integrated circuits SAA2510 video cd (vcd) decoder
1996 may 21 2 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 features (with standard microcode loaded) decoding and display of mpeg1 video streams (constrained parameters) decoding of mpeg audio streams (layer ii) decoding, storage (compressed) and display of high-resolution still pictures of 704 576 pixels requires only 4 mbits of external 70 ns dram audio transparency mode for cd-da discs on-screen display capability play options: C play C stop C pause/continue C slow-motion forward C scan forward C scan backward. supports auto-pause feature disc interface: philips i 2 s, eiaj, mec formats and iec 958 (ebu) interface separate error flag input (efin) and data valid input (ndav) performs basic block decoder functions: C serial-to-parallel conversion C sync detection C descrambling C edc calculation C error-correction for mode 2 form 1 sectors C header and sub-header interpretation. i 2 c-bus interface video output yuv 4:2:2 format. dmsd bus compatible also supports ccir656 video interface, including line and field timing codes audio output: 44.1 khz. 16, 18 or 20 bits per audio sample in philips i 2 s, sony or mec formats ebu audio output, fully transparent from input to output in cd-da mode and generated in mpeg mode downloadable microcode for internal controllers internal video timing generator requires 40 mhz crystal for system clock generation requires 27 mhz crystal or external 27 mhz source for video timing generation requires 16.9344 mhz (384 44.1 khz) clock locked to cd drive internal generation of 90 khz mpeg clock capability of sharing external dram by 3-stating all dram pins. application dedicated video cd players. general description mpeg1 audio and video cd (vcd) decoder, intended for use in low-cost dedicated video cd players. when used with a 4 mbit dram and a digital video encoder, the decoder adds the required functionality to a cd decoder to implement a low-cost video cd player capable of playing discs coded to version 2.0 of the video cd specification. the SAA2510 is an i 2 c-bus controlled chip and features serial data input in four common bus formats. it provides digital video output in ccir601 and 656 formats. a bit-mapped on-screen display is provided and output video timing can be 525 lines/30 frames per second or 625 lines/25 frames per second. the chip is microcode programmable for feature enhancement. ordering information type number package name description version SAA2510 qfp100 plastic quad ?at package; 100 leads (lead length 1.95 mm); body 14 20 2.7 mm; high stand-off height sot317-1
1996 may 21 3 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 quick reference data symbol parameter min. typ. max. unit v dd3 supply voltage 3.0 3.3 3.6 v v dd5 supply voltage 4.5 5.0 5.5 v i dd supply current - tbf - ma f xtal s system clock crystal frequency - 40.0 - mhz f xtal v video clock crystal frequency - 27.0 - mhz f i audio clock input frequency - 16.9344 - mhz t amb operating ambient temperature - 20 -+ 70 c
1996 may 21 4 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 block diagram a ndbook, full pagewidth mge325 block decoder system controller host i 2 c interface data sorter video generator video clock idct video decoder frame recon- structor memory management unit system clock osd buffer external 4 mbit dram audio fifo video fifo video buffer 0 video buffer 1 video buffer 2 play control buffer test control audio decoder ndav sda scl asel int audioclk ebuin wsin efin clin dain sys_osc_1 sys_osc_0 reset cdir 76 77 78 28 14 16 13 12 9 11 cref 80 clk27 82 vid_osc_1 86 vid_osc_0 84 97 74 27 79 a0 to a8 dr0 to dr15 99 vsync href tlsand csync ebuout daout clout wsout tp1 tp2 dramon SAA2510 3 k 7 k cas ras w 8 7 to 1 100 uv0 to uv7 95 to 88 y0 to y7 8 fig.1 block diagram.
1996 may 21 5 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 pinning symbol pin description uv6 1 video uv bus output bit 6; 16-bit video output mode: the uv bus outputs alternating u and v chroma samples at 13.5 mbytes/s ccir656 mode: this bus is not used (inactive) uv5 2 video uv bus bit 5 uv4 3 video uv bus bit 4 uv3 4 video uv bus bit 3 uv2 5 video uv bus bit 2 uv1 6 video uv bus bit 1 uv0 7 video uv bus bit 0 v dd5 8 5 v external pad power supply csync 9 composite sync output; 525 lines/60 hz or 625 lines/50 hz v ss5 10 0 v external pad power supply tlsand 11 two-level sandcastle (composite blanking) output; requires external resistor network to de?ne horizontal/vertical blanking level ebuout 12 iec 958 digital audio output daout 13 i 2 s data; digital audio output wsout 14 i 2 s word select digital audio output v dd3 15 +3 v internal power supply clout 16 i 2 s bit clock output v ss 17 0 v internal power supply audioclk 18 16.9 mhz audio clock input v dd5 19 5 v internal power supply ebuin 20 ebu (iec 958) input clin 21 i 2 s bit clock input wsin 22 i 2 s word select input dain 23 i 2 s digital data input v dd3 24 +3 v internal power supply efin 25 error ?ag input from i 2 s source v ss 26 0 v internal power supply reset 27 active low reset input dramon 28 dram pin 3-state control input; also 3-states video outputs and some timing signals int 29 active low open drain interrupt request to host microcontroller ndav 30 data not valid input (data on i 2 s or ebu input not valid) asel 31 i 2 c-bus address select pin sda 32 i 2 c-bus data pin v dd5 33 5 v external pad power supply scl 34 i 2 c-bus clock input v ss5 35 0 v external pad power supply dr15 36 dram data input/output bit 5
1996 may 21 6 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 dr14 37 dram data input/output bit 14 dr13 38 dram data input/output bit 13 dr12 39 dram data input/output bit 12 dr11 40 dram data input/output bit 11 dr10 41 dram data input/output bit 10 dr9 42 dram data input/output bit 9 v dd5 43 5 v external pad power supply dr8 44 dram data input/output bit 8 v ss5 45 0 v external pad power supply dr7 46 dram data input/output bit 7 dr6 47 dram data input/output bit 6 dr5 48 dram data input/output bit 5 dr4 49 dram data input/output bit 4 dr3 50 dram data input/output bit 3 dr2 51 dram data input/output bit 2 dr1 52 dram data input/output bit 1 dr0 53 dram data input/output bit 0 v ss5 54 0 v external pad power supply cas 55 dram column address strobe v dd5 56 5 v external pad power supply a8 57 dram row/column address pin a8 a7 58 dram row/column address pin a7 a6 59 dram row/column address pin a6 a5 60 dram row/column address pin a5 a4 61 dram row/column address pin a4 v dd3 62 +3 v internal power supply w 63 active low dram write strobe v ss 64 0 v internal power supply ras 65 dram row address strobe v dd5 66 5 v internal power supply a3 67 dram row/column address pin a3 v ss5 68 0 v external pad power supply a2 69 dram row/column address pin a2 v dd5 70 5 v external pad power supply a1 71 dram row/column address pin a1 a0 72 dram row/column address pin a0 v ddo3 73 3 v internal power supply for oscillator sys_osc_0 74 oscillator input pin; 40 mhz oscillator v ss 75 0 v internal power supply sys_osc_1 76 oscillator output pin; 40 mhz oscillator tp1 77 factory test pin; connect to ground symbol pin description
1996 may 21 7 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 tp2 78 factory test pin; connect to ground cdir 79 clock direction control pin; when high, clk27 is an output cref 80 clock quali?er output; 13.5 mhz timing signal used in 16-bit video output mode; can also be used as 13.5 mhz video sample clock v ss5 81 0 v external pad power supply clk27 82 27 mhz clock input or output; direction controlled by cdir pin v dd5 83 5 v external pad power supply vid_osc_0 84 oscillator pin; 27 mhz; input pin v ss 85 0 v internal power supply vid_osc_1 86 oscillator pin; 27 mhz; output pin v ddo3 87 3 v internal power supply for oscillator y7 88 video y bus output bit 7 dmsd mode: the y bus outputs luminance samples at 13.5 mbytes/s ccir656 mode: this pin supplies multiplexed chrominance and luminance (27 mbytes/s) y6 89 video y bus bit 6 y5 90 video y bus bit 5 y4 91 video y bus bit 4 y3 92 video y bus bit 3 y2 93 video y bus bit 2 y1 94 video y bus bit 1 y0 95 video y bus bit 0 v ss5 96 0 v external pad power supply href 97 horizontal (line) timing reference signal; high during active video part of line, low during line blanking v dd5 98 5 v external pad power supply vsync 99 vertical (?eld/frame) timing reference signal; high during vertical blanking interval of ?eld uv7 100 video uv bus output bit 7 dmsd mode: the uv bus outputs alternating u and v chroma samples at 13.5 mbytes/s ccir656 mode: this bus is not used (inactive) symbol pin description
1996 may 21 8 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 fig.2 pin configuration. handbook, full pagewidth 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 cref cdir tp2 tp1 sys_osc_1 v ss sys_osc_0 v ddo3 a0 a1 v dd5 a2 v ss5 a3 v dd5 v ss v dd3 a4 a5 a6 a7 a8 v dd5 v ss5 dr0 dr1 dr2 uv6 uv5 uv4 uv3 uv2 uv1 uv0 v dd5 csync v ss5 tlsand ebuout daout wsout v dd3 clout v ss audioclk v dd5 ebuin clin wsin dain v dd3 efin v ss dramon ndav asel sda v dd5 scl v ss5 dr15 dr14 dr13 dr12 dr11 dr10 dr9 v dd5 dr8 v ss5 dr7 dr6 dr5 dr4 dr3 uv7 vsync v dd5 href v ss5 y0 y1 y2 y3 y4 y5 y6 y7 v ddo3 vid_osc_1 v ss vid_osc_0 v dd5 clk27 v ss5 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mge324 SAA2510 reset int cas w ras
1996 may 21 9 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 functional description block decoder the vcd chip receives mpeg a/v or cd digital audio data from a cd decoder chipset using any one of four common interface formats (philips i 2 s, eiaj, mec or iec 958). the philips i 2 s, eiaj and matsushita input modes use the bit clock (clin), word select (wsin), data (dain) and error flag (efin) inputs. if iec 958 (ebu) input mode is selected, only the ebuin pin needs to be connected. the chip also requires a 16.9 mhz clock input (clin) which is synchronous with the data input from the cd decoder providing the serial data input. the vcd chip contains a block decoder and descrambler which performs error correction on the video cd data track (form 1) sectors and error detection on real-time audio and video tracks where an error correction code is present. in most events, audio output can be in any of the three (i 2 s, eiaj or mec) formats, independent of input type. when playing cd digital audio discs, the input is copied to the outputs. the block decoder supports some special functions which enable recovery of play control lists. the desired sectors can be acquired by programming a sector address via the i 2 c-bus microcontroller interface. the microcontroller then instructs the cd servo/decoder subsystem to execute a servo jump to the required disc location and then waits for an interrupt indicating that the desired sector information has been received and error-corrected. system controller overall control of the chip and a number of its less time-critical functions is carried out by a dedicated risc processor. the microcode for this processor is executed from an on-chip ram. this microcode must be loaded into ram after power-up by the host microcontroller, using the i 2 c-bus interface. this enables the functionality of the chip to be customized for specific applications. on-screen display the vcd chip provides a bit-mapped on-screen-display (osd), containing 32 display lines of 352 pixels per line. there is a double-height mode which repeats osd lines so that the maximum height of osd objects becomes 64 lines. this character-set-independent osd permits display of ideographic characters and simple graphic displays anywhere on the screen. the osd is implemented as 48 vertical slices of 8 pixels (horizontally) and 32 (vertically). each pixel is stored as 2 bits. this gives three programmable logical colours, plus a transparent option. each slice is identified by a slice code (slice number). the horizontal position of a slice is defined by its position in a slice code sequence written to the vcd chip. this arrangement reduces the need to completely update the osd bit map in many situations. it may be possible to simply reorder the slices, e.g. if a track time display is being updated and slices are prepared to represent digits. at any time, up to 44 of the 48 slices can be displayed. video decoder video output data can be presented in one of two modes: 1. 16-bit wide data is output in yuv 4 : 2 : 2 format as 8 bits of luminance and 8 bits of alternating u and v chrominance. the video output data rate in this mode is 13.5 mwords/s. 2. 8-bit wide, ccir656-like, data is output providing 4:2:2 format video as an 8-bit uyvy multiplex at 27 mbytes/s. in either case, the vcd chip can be programmed to output 525 line or 625 line format timing to match the type of display (tv) connected to its output. additional programmability is provided to cope with the video cd disc source picture coding type (525/625 lines). the vcd chip performs vertical and horizontal interpolation to convert the mpeg sif (352 pixels per line) normal resolution pictures to ccir601 resolution. vertically interpolated pixels are output on the odd fields during display of normal resolution pictures. the video cd disc being played may have been coded with 525 lines/60 hz or 625 lines/50 hz pictures. when the video cd player is connected to a display with a different timebase to the coded disc material, some adjustments must be made to allow for the different number of lines on the display and the reconstructed picture. two examples are shown in figs. 3 and 4. the vcd chip can be programmed to position the reconstructed picture with respect to horizontal and vertical syncs anywhere on the display screen with a programmable viewport position. figure 3 shows an mpeg sif resolution picture (352 pixels by 288 lines) being displayed on an ntsc display having only 240 active display lines per field. in this event, the top and bottom 24 lines are not displayed.
1996 may 21 10 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 the second example, illustrated in fig.4, is where a 240 active lines per field ntsc picture needs to be displayed on a 288 line pal format display. the missing lines can be filled with a programmable border colour. high-resolution still pictures can be present on a video cd disc. in this event, the horizontal and vertical resolution of the reconstructed picture is double that of normal resolution (moving) pictures. in order to fit the picture in the available frame buffer dram, a data compression scheme is applied to the stored picture. fig.3 one field of a 625-line picture on a 525-line display. handbook, halfpage mge332 reconstructed picture window reconstructed picture 352 not displayed not displayed 24 24 240 288 fig.4 525-line picture on a 625-line display. handbook, halfpage mge333 viewport display window 352 border = blank border = blank 240 288
1996 may 21 11 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 trickmode implementation compared with cd digital audio players, it is likely that video cd players will need to offer additional functionality similar to vcrs. these features are commonly called trickmodes. typically, the player will offer features such as still picture (freeze frame), scan forwards and backwards as well as slow motion replay. these features require a combination of cd servo control and video cd decoder functions for effective implementation. the vcd chip provides high level command features to support these modes in order to minimize microcontroller time-critical software. s till picture display this is implemented directly using a pause command, causing the vcd chip to hold the displayed picture at the next frame update. s can forward and scan backwards there is no difference as far as the vcd chip is concerned. the controlling microcomputer must command the cd servo to execute a servo jump and re-synchronize. the vcd chip is then commanded to display the next i (intra-coded) picture following re-acquisition of sector sync. s low - motion replay a command is provided by the vcd chip, allowing a slow-motion factor in the range 2 to 8 to be selected. this is the factor by which replay will be slowed down. because the rate of decoding of video sectors has been reduced, the video fifo fills up. the block decoder is designed to automatically disable acquisition when the video fifo fills in this way and an interrupt is generated. at this point, the next wanted sector (address) has been loaded into a register in the vcd chip. the controlling microcomputer then commands a cd servo jump to position on the disc just before the next desired sector, making allowance for re-synchronization by the servo and vcd chip. i 2 c-bus interface the vcd chip is programmed via the i 2 c-bus interface. the chip is a slave transceiver capable of operating at the maximum specified bus clock frequency of 400 khz. it does not support the general call feature. one of two slave addresses can be used. the address is selected by the asel input pin. this bus provides access to the internal registers of the device. the bus is also used to write osd slice data and to read data stored in three play-control sector buffers, which normally will be used to store video cd data track information. this interface features a two or three byte sub-addressing scheme allowing access to any dram location. however, in normal use, only two byte sub-addressing is needed. an interrupt pin is available to signal a number of events so that the controlling processor does not need to poll vcd status registers. input pin ndav is used to signal that data on the block decoder input is not valid, e.g. during cd servo jumps. a complete memory map and list of registers will be included in a later version of this data sheet. i 2 c-bus slave address selection note 1. asel. the data transfer protocol is as follows: two and three byte sub-addressing: first the device sub-address is transmitted, preceded by a start condition and the slave address: two and three byte sub-addressing the sub-address can be either 2 or 3 bytes. the 3-byte sub-address is used for dram random access. this is not used for normal operation. it exists only as a test mode. since the video cd ic is internally fully word (16 bits) oriented, the sub-address must always be an even address. if an odd-numbered address is given, the video cd ic will not acknowledge this byte. for the sub-address, the least significant byte is sent first. the second sub-address byte contains 2 control bits. a6 a5 a4 a3 a2 a1 a0 r/w 001101a0 (1) s sla w sub_a s = start sla = slave address w = write sub_a = sub-address
1996 may 21 12 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 sub-address byte format msb lsb msb lsb a7 a6 a5 a4 a3 a2 a1 a0 c1 c0 a13 a12 a11 a10 a9 a8 when a0 is a 1, the address byte is not acknowledged (odd address). explanation of control bits c0 = 0; 2-byte sub-address. c0 = 1; 3-byte sub-address. the next byte transmitted is also an address byte: 3-byte sub-address - most signi?cant byte format c1 = 0; sub-address post increment enabled. after each transfer of 2 bytes, the address is automatically incremented by 2. c1 = 1; sub-address post increment disabled. the master will terminate a read action by not acknowledging the last read byte followed by a stop condition. msb lsb 0 0 0 a18 a17 a16 a15 a14 i 2 c-bus transaction summary the following notation is used to describe bus transactions: s: start condition generated by bus master p: stop condition generated by bus master a: acknowledge bit generated by master or slave according to transaction type and stage n: negative acknowledge; acknowledge bit is not set by bus master during last byte of a read sla: 7-bit slave address generated by bus master w: r/w bit after slave address is set to write r: r/w bit after slave address is set to read sub_n: sub-address byte n (n = 0, 1 or 2); least significant address byte is sub_0 d(m): a data byte transmitted by master or slave on the bus; d(0) is the first byte sent; as all transfers must be an even number of bytes, it follows that m must be odd. set 2-byte sub-address and write (m + 1) bytes set 2-byte sub-address and read (m + 1) bytes set 3-byte sub-address and write (m + 1) bytes set 3-byte sub-address and read (m + 1) bytes this addressing mode is valid only if sub-address auto incrementing is disabled. it is intended for fast polling of a status register. s sla w a sub_0 a sub_1 a d(0) a d(1) a to d(m) a p s sla w a sub_0 a sub_1 a s sla r d(0) a d(1) a to d(m) n p s sla w a sub_0 a sub_1 a sub_2 a d(0) a d(1) a to d(m) a p s sla w a sub_0 a sub_1 a sub_2 a s sla r a d(0) a d(1) a to d(m) n p
1996 may 21 13 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 byte-order within words for each transmitted word (read or written) the least significant byte is transmitted first. characteristics t amb = - 20 to + 70 c; v dd5 = 4.5 to 5.5 v; v dd3 = 3.0 to 3.6 v; unless otherwise speci?ed. lsb msb word b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 i 2 c-bus b7 b6 b5 b4 b3 b2 b1 b0 b15 b14 b13 b12 b11 b10 b9 b8 symbol parameter conditions min. typ. max. unit supplies v dd5 supply voltage (5 v) range 4.5 5 5.5 v i dd5 v dd5 supply current - tbf tbf ma v dd3 supply voltage (3 v) range 3 3.3 3.6 v i dd3 v dd3 supply current - tbf tbf ma i dd(tot) total supply current - tbf tbf ma digital inputs a ll inputs ( except reset and oscillator inputs ) v il low level input voltage - 0.3 -+ 0.8 v v ih high level input voltage 2 - v dd + 0.5 v i li input leakage current v i =0tov dd - 10 -+ 10 m a c i input capacitance -- 10 pf reset input :(s chmitt input ) v il low level input voltage - 0.3 + 2v v ih high level input voltage 3.5 v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 + 10 m a v hys hysteresis voltage (v ih - v il ) 1 -- v inputs/outputs sda and scl (i 2 c- bus data and clock ) v il low level input voltage - 0.5 -+ 1.5 v v ih high level input voltage 3 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 -+ 10 m a c i input capacitance -- 10 pf c l load capacitance -- 400 pf v ol low level output voltage (i ol = 3.0 ma) 0 - 0.4 v v ol low level output voltage (i ol = 6.0 ma) 0 - 0.6 v clk27 v il low level input voltage - 0.3 -+ 0.8 v v ih high level input voltage 2.4 - v dd + 0.5 v
1996 may 21 14 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 i li input leakage current v i = 0 to v dd - 10 -+ 10 m a c i input capacitance -- 10 pf v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v v oh high level output voltage (i oh = - 0.2 ma) 2.6 - v dd v t r input rise time 0.6 to 2.6 v -- 4ns t f input fall time 0.6 to 2.6 v -- 4ns dr15 to dr0 (dram data i / o ) v il low level input voltage - 0.3 -+ 0.8 v v ih high level input voltage 2 - v dd + 0.5 v i li input leakage current v i = 0 to v dd - 10 -+ 10 m a c i input capacitance -- 10 pf c l load capacitance -- 30 pf v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v v oh high level output voltage (i oh = - 0.2 ma) 2.4 - v dd v t r output rise time 0.6 to 2.6 v; load = c l 3 - 10 ns t f output fall time 0.6 to 2.6 v; load = c l 3 - 10 ns outputs ras, cas, w, a0 to a8 (dram control and address lines ) v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v v oh high level output voltage (i oh = - 0.2 ma) 2.4 - v dd v c l load capacitance - 30 pf t r output rise time 0.6 to 2.2 v; load = c l 3 - 10 ns t f output fall time 0.6 to 2.2 v; load = c l 3 - 10 ns y0 to y7 ( video output y bus ) v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v v oh high level output voltage (i oh = - 0.2 ma) 2.4 - v dd v c l load capacitance -- 30 pf t r output rise time 0.6 to 2.6 v; load = c l -- 4ns t f output fall time 0.6 to 2.6 v; load = c l -- 4ns uv0 to uv7 ( video output uv bus ) v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v v oh high level output voltage (i oh = -0.2 ma) 2.4 - v dd v c l load capacitance -- 30 pf t r output rise time 0.6 to 2.2 v; load = c l -- 10 ns t f output fall time 0.6 to 2.2 v; load = c l 3 - 10 ns int ( open drain ; interrupt ) v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v c l load capacitance -- 30 pf t r output rise time 0.6 to 2.2 v; load = c l -- 10 ns symbol parameter conditions min. typ. max. unit
1996 may 21 15 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 t f output fall time 0.6 to 2.2 v; load = c l -- 10 ns ebuout (iec 958 out ) v ol low level output voltage (i ol = 10 ma) 0 - 1v v oh high level output voltage (i oh = - 10 ma) v dd5 - 1 - v dd v c l load capacitance -- 50 pf t r output rise time 0.8 v to (v dd5 - 0.8 v); load = c l -- 10 ns t r output fall time 0.8 v to (v dd5 - 0.8 v); load = c l -- 10 ns a ll other inputs v ol low level output voltage (i ol = 1.6 ma) 0 - 0.4 v v oh high level output voltage (i oh = - 0.2 ma) 2.4 - v dd v c l load capacitance -- 50 pf t r output rise time 0.6 to 2.6 v; load = c l -- 30 ns t f output fall time 0.6 to 2.6 v; load = c l -- 30 ns i 2 s input/output timing; (fig.5) i nput timing f clk input clock frequency - 2.118 - mhz t clkh input clock high period 166 -- ns t clkl input clock low period 166 -- ns t su set-up time (dain, efin, wsin) 95 -- ns t h1 hold time dain, efin, wsin) 0 -- ns o utput timing f clk output clock frequency - 2.118 - mhz t clkh output clock high period 166 -- ns t h2 hold time (daout, wsout) 195 -- ns t d output delay time (daout, wsout) -- 147 ns i 2 c-bus input/output timing (fig.6) 100 khz clock frequency f clk clock frequency 0 - 100 khz t low clock low period 4.7 -- m s t high period 4 -- m s t su;dat data set-up time 250 -- ns t hd;dat data hold time 0 -- ns t su;sto set-up time clock high to stop 4.7 -- m s symbol parameter conditions min. typ. max. unit
1996 may 21 16 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 t buf set-up time stop to start 4.7 -- m s t hd;sta start hold time 4 -- m s t su;sta set-up time clock rising edge to start 4.7 -- m s t r rise time (sda and scl) v ilmin to v ihmax 50 - 1000 ns t f fall time (sda and scl) v ilmin to v ihmax 50 - 300 ns 400 khz clock frequency f clk clock frequency 0 - 400 khz t low clock low period 1.3 -- m s t high period 0.6 -- m s t su;dat data set-up time 100 -- ns t hd;dat data hold time 0 -- ns t su;sto set-up time clock high to stop 0.6 -- m s t buf set-up time stop to start 1.3 -- m s t hd;sta start hold time 0.6 -- m s t su;sta set-up time clock rising edge to start 0.6 -- m s t r rise time (sda and scl) v ilmin to v ihmax 50 - 300 ns t f fall time (sda and scl) v ilmin to v ihmax 50 - 300 ns video output timing (figs. 7 and 8) 16- bit video output mode t su set-up time (cref, href, uv and y valid to clk27) 10 -- ns t h2 hold time (clk27 to cref, href, uv and y invalid) 3 -- ns t su set-up time (uv and y valid to cref rising edge) 6 -- ns t h1 hold time (cref rising edge to uv and y invalid) 10 -- ns 8- bit video output mode t su set-up time (href and y valid to clk27) 7 -- ns t h2 hold time (clk27 to href and y invalid) 5 -- ns dram timing (fig.9) t cyc cycle time 130 -- ns t rp ras pre-charge time 50 -- ns t csh cas hold time 70 -- ns t rcd ras to cas delay time 20 -- ns symbol parameter conditions min. typ. max. unit
1996 may 21 17 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 t cas cas pulse width low 20 -- ns t pc page mode cycle time 50 -- ns t cp cas pre-charge time 10 -- ns t rsh ras hold time after cas 20 -- ns t crp cas to ras pre-charge time 15 -- ns t asr row address set-up time 0 -- ns t rah row address hold time 10 -- ns t asc column address set-up time 0 -- ns t cah column address hold time 15 -- ns t rcs read command set-up time 0 -- ns t rch read command hold time ( cas) 0 -- ns t rrh read command hold time ( ran) 0 -- ns t wcs write command set-up time 0 -- ns t wch write command hold time 15 -- ns t ds data-in set-up time 0 -- ns t dh data-in hold time 15 -- ns t cac read access time ( cas) -- 20 ns t rac read access time ( ras) -- 70 ns crystal oscillators 40 mhz system clock oscillator v osc(p-p) oscillation amplitude (peak-to-peak) - tbf - v g v small signal voltage gain - tbf - g m mutual conductance tbf -- ma/v c i input capacitance -- tbf pf c fb feedback capacitance - tbf - pf f osc oscillation frequency - 40 - mhz d f frequency tolerance --- ppm 27 mhz system clock oscillator v osc(p-p) oscillation amplitude (peak-to-peak) - tbf - v g v small signal voltage gain - tbf - g m mutual conductance tbf -- ma/v c i input capacitance -- tbf pf symbol parameter conditions min. typ. max. unit
1996 may 21 18 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 c fb feedback capacitance - tbf - pf f osc oscillation frequency - 27 - mhz d f frequency tolerance --- ppm symbol parameter conditions min. typ. max. unit fig.5 i 2 s input/output timing. handbook, full pagewidth mge327 i 2 s bit clock clkin or clkout i 2 s data and word select outputs daout, wsout i2s data, word select and error flags inputs dain, wsin, efin t clkh t clkl t h t d t h t su fig.6 i 2 c-bus timing. handbook, full pagewidth mge328 t su; sta t hd; sta t high t low t r t f t hd; dat t su;sto t su; dat scl sda t buf
1996 may 21 19 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 fig.7 16-bit video output mode timing. timing applies to clk27 when programmed as an input or an output of the SAA2510. (1) csync (high-to-low) to first sample and href (low-to-high) = 264.5/244.5 clk27 periods (625 lines/525 lines mode). handbook, full pagewidth mge329 (1) t su2 t h1 t h2 t h2 t h1 t su t su1 27 mhz clock (clk27) cref href csync u0 (cb0) v0 (cr0) y0 y1 pixel #0 v718 y719 pixel #719 fig.8 8-bit video ccir656 output mode timing. handbook, full pagewidth mge330 t su t h1 t h2 27 mhz clock (clk27) href y bus output y719 pixel #719 cb cr y pixel #0
1996 may 21 20 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 fig.9 dram timing. handbook, full pagewidth mge331 read cycle write cycle vcd data to dram dram data out address cas ras w w t dh t ds t wcs t wch t rac t cac t rrh t rcs t rch t asc t rah t cah t asr t pc t cp t rcd t cas t csh t crp t rsh t cyc t rp
1996 may 21 21 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 application information fig.10 application diagram; 16-bit video output mode. vcd power supply pins not shown. handbook, full pagewidth mge326 ebuin ebu input sys_osc_0 sys_osc_1 audioclk clin dain wsin esin dr0 to dr15 a0 to a8 casn rasn w vp0 to 7 cvbs audio l, r y, c i 2 c-bus i 2 c-bus cref e.g.: saa7185 llc asel sda scl reset ndav intn dramon ebuout clout daout wsout cref test1, 2 SAA2510 40 mhz crystal clk27 cdir href vsync uv0 to 7 y0 to 7 4 mbit dram microcontroller and user interface compact disc mechanism and decoder 2 0 v 27 mhz crystal vid_osc_0 vid_osc_1 0 v 0 v digital video encoder audio dac ebu interface 8 16 9 8 + 5 v
1996 may 21 22 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.36 0.10 2.87 2.57 0.25 0.40 0.25 0.25 0.13 14.1 13.9 0.65 18.2 17.6 1.0 0.6 7 0 o o 0.15 1.95 0.1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 1.0 0.6 sot317-1 95-02-04 97-08-01 d (1) (1) (1) 20.1 19.9 h d 24.2 23.6 e z 0.8 0.4 d b p e q e a 1 a l p detail x l (a ) 3 b 30 c d h b p e h a 2 v m b d z d a z e e v m a 1 100 81 80 51 50 31 pin 1 index x y w m w m 0 5 10 mm scale a max. 3.3 100 leads (lead length 1.95 mm); body 14 x 20 x 2.7 mm; high stand-off height qfp100: plastic quad flat package; sot317-1
1996 may 21 23 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all qfp packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference handbook (order code 9397 750 00192). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 may 21 24 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 may 21 25 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 notes
1996 may 21 26 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 notes
1996 may 21 27 philips semiconductors preliminary speci?cation video cd (vcd) decoder SAA2510 notes
philips semiconductors C a worldwide company argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. (02) 805 4455, fax. (02) 805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. (01) 60 101-1256, fax. (01) 60 101-1250 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. (172) 200 733, fax. (172) 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. (359) 2 689 211, fax. (359) 2 689 102 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: see south america china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852) 2319 7888, fax. (852) 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (032) 88 2636, fax. (031) 57 1949 finland: sinikalliontie 3, fin-02630 espoo, tel. (358) 0-615 800, fax. (358) 0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01) 4099 6161, fax. (01) 4099 6427 germany: p.o. box 10 51 40, 20035 hamburg, tel. (040) 23 53 60, fax. (040) 23 53 63 00 greece: no. 15, 25th march street, gr 17778 tavros, tel. (01) 4894 339/4894 911, fax. (01) 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, bombay 400 018 tel. (022) 4938 541, fax. (022) 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. (01) 7640 000, fax. (01) 7640 200 israel: rapac electronics, 7 kehilat saloniki st, tel aviv 61180, tel. (03) 645 04 44, fax. (03) 648 10 07 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. (0039) 2 6752 2531, fax. (0039) 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. (03) 3740 5130, fax. (03) 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02) 709-1412, fax. (02) 709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03) 750 5214, fax. (03) 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. 9-5(800) 234-7831, fax. (708) 296-8556 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040) 2783749, fax. (040) 2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09) 849-4160, fax. (09) 849-7811 norway: box 1, manglerud 0612, oslo, tel. (022) 74 8000, fax. (022) 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. (022) 612 2831, fax. (022) 612 2327 portugal: see spain romania: see italy singapore: lorong 1, toa payoh, singapore 1231, tel. (65) 350 2000, fax. (65) 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. (011) 470-5911, fax. (011) 470-5494 south america: rua do rocio 220 - 5th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011) 821-2333, fax. (011) 829-1849 spain: balmes 22, 08007 barcelona, tel. (03) 301 6312, fax. (03) 301 4107 sweden: kottbygatan 7, akalla. s-16485 stockholm, tel. (0) 8-632 2000, fax. (0) 8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01) 488 2211, fax. (01) 481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey : talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0212) 279 2770, fax. (0212) 282 6707 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181) 730-5000, fax. (0181) 754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800) 234-7381, fax. (708) 296-8556 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. (381) 11 825 344, fax. (359) 211 635 777 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31-40-2724825 scds48 ? philips electronics n.v. 1996 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 537021/1200/01/pp28 date of release: 1996 may 21 document order number: 9397 750 00851

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